Caching RISC-V Example

Abstract

This activity allows students to explore aspects of caching including spatial and temporal locality, the relationship of a memory reference stream to an assembly language program (specifically RISC-V), hand simulating a direct mapped cache, and exploring the impact of a cache on performance. Level: Upper level undergraduate. Setting: Classroom Activity Type: Learning Cycle Discipliine: Computer Science Course: Computer Architecture. Keywords: caching, locality, performance, memory reference streams, RISC-V